The following analysis on the related art is presented by the present invention.
In CMOS circuits, a phenomenon referred to as a phenomenon called as “latchup” sometimes happens. In this phenomenon, a thyristor is formed by a pair of an npn bipolar transistor and a pnp bipolar transistor generated accompanied by the structures of nMOS transistor and pMOS transistor and well(s), and this thyristor turns on by noise or the like. FIG. 5 is a sectional view schematically showing a structure of a semiconductor integrated circuit device including a CMOS circuit, as an example. Referring to FIG. 5, in the semiconductor integrated circuit device, a deep n well 120, a p well 121, and an n well 122 are formed in a p substrate 110. The p well 121 includes n+ diffusion layers 125 and 126. Together with a gate electrode 127a, the n+ diffusion layers 125 and 126 form an nMOS transistor. The p well 121 further includes a p+ diffusion layer 151. A back bias control circuit 140a supplies a back bias to the p well 121 via the p+ diffusion layer 151. Further, the n+ diffusion layer 126 that corresponds to a source of the nMOS transistor is connected to ground GND.
On the other hand, the n well 122 includes p+ diffusion layers 128 and 129. Together with a gate electrode 127b, the p+ diffusion layers 128 and 129 form a pMOS transistor. The n well 122 includes an n+ diffusion layer 152. A back bias control circuit 140b supplies a back bias to the n well 122 via the n+ diffusion layer 152. The p+ diffusion layer 129 that corresponds to a source of the pMOS transistor is connected to a power supply VDD. Further, a device separation region 115 is provided between the respective diffusion layers.
In the semiconductor integrated circuit device having such a structure, the n well 122, p well 121, and n+ diffusion layer 126 form an npn bipolar transistor Q1. The p well 121, n well 122, and p+ diffusion layer 129 form a pnp bipolar transistor Q2. Then, the npn bipolar transistor Q1 and the pnp bipolar transistor Q2 form a thyristor. When this thyristor turns on by noise or the like and the latchup occurs, a large short-circuit current Is will flow from the power supply VDD to the ground GND. An operation of the semiconductor integrated circuit device itself will thereby become unstable. Accordingly, it is important to prevent occurrence of the latchup as described above.
By the way, the latchup as described above tends to occur at such a time as power-on when a voltage is not stabilized. Each of the back bias control circuits 140a and 140b, in particular, is often configured to supply the voltage boosted by a charge pump circuit or the like. Thus, each of the back bias control circuits 140a and 140b does not always supply a sufficiently stable voltage, as a power supply path. Then, Patent Document 1 discloses a semiconductor integrated circuit that prevents a latchup phenomenon at the time of power-on. This semiconductor integrated circuit is configured so that when a ground potential is employed as a low potential VSS, a power supply terminal that supplies the low potential VSS and a p-type region that forms an n-channel MOS transistor are short circuited from start of a power supply potential VDD is supplied until a bias circuit is operated; and then after the bias circuit starts operation, the power supply terminal and the p-type region are disconnected to supply a negative potential to the p-type region. Accordingly, a potential at the P-type region with which the n-channel type MOS transistor is formed will not transiently rise to a positive potential, and application of a voltage in a forward direction will not be applied across the n-type source region and the p-type region. The latchup can be thereby prevented.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-8-37283